16-04-2021 | X-FAB | Automotive Technologies
X-FAB Silicon Foundries offers a new Flash memory capability for its XP018 high-voltage automotive process. This new Flash IP leverages the company’s already widely proven SONOS technology, which provides a mixture of elevated levels of performance and best-in-class reliability. Fully compliant with stringent AEC100-grade 0 automotive specification, it is able to withstand operation over a -40C to 175C temperature range and wholly supports the functional safety levels specified by ISO 26262.
Complementary metal–oxide–semiconductor (CMOS), also known as complementary-symmetry metal–oxide–semiconductor (COS-MOS), is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions. 0.13-µm technology node for complementary MOSFET (CMOS) is used for very large scale ICs (VLSIs) and, within a few years, sub-0.1-µm technology will be available, with a commensurate increase in speed and in integration scale.
It is supplied in a 32KB array size, following an 8K x 39-bit configuration, with a 32-bit data bus. A further seven bits are dedicated to ECC so that zero-defect reliability in the field is assured. X-FAB’s proprietary XSTI embedded NVM IP test interface has also been included to enable full serial access to the memory.
As this automotive-grade Flash IP can run on a single 1.8V power supply, it is ideal for low-power designs. The addition of a BIST module is pivotal in facilitating effective memory testing, as well as allowing comprehensive product debugging. The company is also able to give a full NVM test service to customers if required.
“This new IP solution further enriches X-FAB’s embedded Flash portfolio for 180 nm open technology platforms, which come with a large selection of voltages and wafer materials. This strengthens our offering to the market, allowing us to meet customer demands across a wider variety of applications,” states Thomas Ramsch, director NVM Development at X-FAB. “It will be of particular value in situations where both low-power and resilience to challenging conditions are expected.”
“By being able to complement existing X-FAB platforms with new embedded Flash capabilities, our customers will benefit from significant reductions in footprint. Also, the modular approach of XP018 means that fewer mask layers are going to be needed. Both these factors will help with realising major die cost optimisation,” adds Nando Basile, technology marketing manager for NVM solutions at X-FAB.
“The new Flash IP means that XP018 is now able to address mixed-signal, high-voltage applications where additional logic content and computational resources are required in a highly cost-effective way. This will specifically benefit battery-operated devices, such as portable or autonomous smart sensors, with a great deal of potential in healthcare, industrial, consumer and IoT sectors.”
LATEST MODELS
Typical SPICE model files for each future generation are available here.
Attention: By using a PTM file, you agree to acknowledge both the URL of PTM: http://ptm.asu.edu/and the related publicationsin all documents and publications involving its usage.
New!
June 01, 2012:
PTM releases Mega cloud for mac. a new set of models for multi-gate transistors (PTM-MG), for both HP and LSTP applications. It is based on BSIM-CMG, a dedicated model for multi-gate devices.
Mosfet Cmos Process
Fosmon mini bluetooth keyboard. Acknowledgement: PTM-MG is developed in collaboration with ARM.
Please start from models and param.inc.
- 7nm PTM-MG HP NMOS, HP PMOS, LSTP NMOS, LSTP PMOS
- 10nm PTM-MG HP NMOS, HP PMOS, LSTP NMOS, LSTP PMOS
- 14nm PTM-MG HP NMOS, HP PMOS, LSTP NMOS, LSTP PMOS
- 16nm PTM-MG HP NMOS, HP PMOS, LSTP NMOS, LSTP PMOS
- 20nm PTM-MG HP NMOS, HP PMOS, LSTP NMOS, LSTP PMOS
The entire package is also available here: PTM-MG
November 15, 2008:
PTM releases a new set of models for low-power applications (PTM LP), incorporating high-k/metal gate and stress effect.
- 16nm PTM LP model: V2.1
- 22nm PTM LP model: V2.1
- 32nm PTM LP model: V2.1
- 45nm PTM LP model: V2.1
September 30, 2008:
PTM releases a new set of models for high-performance applications (PTM HP), incorporating high-k/metal gate and stress effect.
- 16nm PTM HP model: V2.1
- 22nm PTM HP model: V2.1
- 32nm PTM HP model: V2.1
- 45nm PTM HP model: V2.1
February 29, 2008:
PTM releases the model for metallic carbon nanotube (CNT-interconnect).
- Verilog-A based model card for CNT-interconnect is available at post-si
October 29, 2007:
PTM releases a new version for sub-45nm bulk CMOS, providing new modeling features of metal gate/high-k, gate leakage, temperature effect, and body bias.
Cmos Mosfet Transistor
- 22nm PTM model for metal gate/high-k CMOS: V2.0
- 32nm PTM model for metal gate/high-k CMOS: V2.0
- 45nm PTM model for metal gate/high-k CMOS: V2.0
July 30, 2007
PTM extends the effort to post-Si devices. The first release is for carbon nanotube FET (CNT-FET).
- Verilog-A based model card for CNT-FET is available at post-si
December 15, 2006
PTM for bulk CMOS is released, for 22nm node.
- 22nm BSIM4 model card for bulk CMOS: V1.0
February 22, 2006
A new generation of PTM for bulk CMOS is released, for 130nm to 32nm nodes. It captures the latest technology advances and achieves better scalability and continuity across technology nodes.
- 32nm BSIM4 model card for bulk CMOS: V1.0
- 45nm BSIM4 model card for bulk CMOS: V1.0
- 65nm BSIM4 model card for bulk CMOS: V1.0
- 90nm BSIM4 model card for bulk CMOS: V1.0
- 130nm BSIM4 model card for bulk CMOS: V1.0
September 30, 2005
- 32nm BSIM4 model card for bulk CMOS: V0.0
- 32nm sub-circuit model for FinFET (double-gate): V0.0
- 45nm sub-circuit model for FinFET (double-gate): V0.0 [for better convergence in the simulation, you can initialize the node voltage when using PTM for FinFET]
July 31, 2002 Music editor for mac.
- 45nm BSIM4 model card for bulk CMOS: V0.0
- 65nm BSIM4 model card for bulk CMOS: V0.0
May 31, 2001
- 90nm BSIM3 model card for bulk CMOS: V0.0
- 130nm BSIM3 model card for bulk CMOS: V0.0
- 180nm BSIM3 model card for bulk CMOS: V0.0
References
- S. Sinha, G. Yeric, V. Chandra, B. Cline, Y. Cao, 'Exploring sub-20nm FinFET design with predictive technology models,' to be published at DAC, 2012.
- A. Balijepalli,
- W. Zhao, Y. Cao, 'New generation of Predictive Technology Model for sub-45nm early design exploration,' IEEE Transactions on Electron Devices, vol. 53, no. 11, pp. 2816-2823, November 2006.
- Y. Cao, T. Sato, D. Sylvester, M. Orshansky, C. Hu, 'New paradigm of predictive MOSFET and interconnect modeling for early circuit design,' pp. 201-204, CICC, 2000.